Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process

ABSTRACT

A description is given of two versions of an integrated structure in the emitter switching configuration comprising a high-voltage bipolar power transistor on a low-voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N-epitaxial layer and partly in a second N epitaxial layer; the MOS is located above the emitter region. The bipolar is thus completely buried active sturcture. In the horizontal MOS version, in a N-epitaxial layer there are two P+regions, the tint, which constitutes the base of the bipolar transistor, receives the N+emitter region of the same transistor; the second receives two N+regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.

.Iadd.This is a continuation of application Ser. No. 08/152,959, filedNov. 12, 1993 now abandoned, which is a Reissue of 07/288,405 filed Dec.21, 1988, now U.S. Pat. No. 5,065,213..Iaddend.

FIELD OF THE INVENTION

This invention relates to an integrated high-voltage bipolar powertransistor and low-voltage MOS power transistor structure in an emitterswitiching configuration and to a manufacturing process therefore.

BACKGROUND OF THE INVENTION

Emitter switching is a circuit configuration in which a low-voltagepower transistor (typically an MOS transistor) cuts off the emittercurrent of a high-voltage power transistor (typically a bipolartransistor) in order to switch it off. This configuration, which upuntil now was obtained by means of discrete components, offers thefollowing advantages:

it increases the strength of bipolar transistor as far as thepossibility of inverted secondary ruptures (ESB) occurring areconcerned;

it combines the current and voltage carrying capacity of a pilotedtransistor and the high speed of a low-voltage transistor; and

it enables the system to be piloted directly with linear logic circuits,through the MOS gate.

OBJECT OF THE INVENTION

In view of the advantages that an integrated circuit generally offers,as compared to an analog circuit obtained by means of discretecomponents, the object of this invention is to provide a high-voltagebipolar power transistor and a low-voltage MOS power transistor,connected together in the emitter switching configuration, andintegrated in a single chip of semiconductor material.

SUMMARY OF THE INVENTION

The integrated high-voltage bipolar power transistor and verticallow-voltage MOS power transistor structure, in the emitter switchingconfiguration of the invention comprises:

an N+ type semiconductor substrate,

an overlying semiconductor layer,

a first P type region buried in the aforesaid layer,

a second P type region connecting the first aforesaid region on thesurface, the first and second region constituting the base region of thebipolar transistor, and

a third N+ type region adjoining the aforesaid first region from belowand constituting the emitter region of the bipolar transistor.

According to the invention the semiconductor layer consists of a firstN-type epitaxial layer and a second N-type epitaxial layer grown on it,the first region is located in the first epitaxial layer, in thevicinity of the surface adjacent to the second epitaxial layer, and thesecond region is located in the second epitaxial layer. The third regioncan consist of a completely buried layer located astride between theboundary of the first and second epitaxial layer, the body and sourceregions of the MOS can be located in the second epitaxial layer, in thevicinity of its surface and above the third region. The drain region ofthe MOS consists substantially of the region between the third regionand the aforesaid body regions. Alternatively an integrated high-voltagebipolar power transistor and horizontal low-voltage MOS power transistorstructure, in the emitter switching configuration comprises:

an N+ type semiconductor substrate,

an N- type expitaxial layer grown on the substrate,

a first P+ type region, constituting the base of the bipolar transistor,located in the layer in the vicinity of its surface, and

a second N+ type region, constituting the emitter of the bipolartransistor, adjoining the aforesaid first region from below and from theside and adjoining the surface of the layer from above. According to theinvention in the N- type epitaxial layer and in the vicinity of itssurface there is a third P+ conductivity region as well as a fourth anda fifth N+ type region. These latter regions constitute the MOS sourceand gate regions respectively and being adjacent from below and from theside to the aforesaid third region. The metal coatings of the MOStransistor drain and of the bipolar transistor emitter areinterconnected by means of tracks of conductor material.

A process for manufacturing an integrated high-voltage bipolar powertransistor and vertical low-voltage MOS power transistor structure, inthe emitter switching configuration is characterized by the fact that:

a second N conductivity epitaxial layer, designed to constitute thedrain region of the MOS transistor and at the same time automaticallyform the connection between the drain of the MOS transistor and theemitter of the bipolar transistor, is grown on the first epitaxiallayer,

the body, the source and the gate of the MOS transistor are then createdin the second epitaxial layer, by means of the known processes, incorrespondence with the aforesaid buried emitter zone of the bipolartransistor, and

a P+ type region, which enables the base region of the bipolartransistor to be electrically connected on the surface, is also createdat the side of said MOS transistor, by means of the known techniques ofoxidation, photomasking, implantation and diffusion.

Alternatively, the process is characterized in that:

a second P+ type region, separated from the first by a region of theepitaxial layer, is created in the epitaxial layer simultaneously tosaid first region,

a fourth and a fifth N+ type region, designed to constitute the MOSsource and drain region respectively, are created within the secondregion, and

the deposition of tracks of conductor material designed to electricallyinterconnect the emitter and drain metal coatings is carried outsimultaneously to the deposition of the films of conductor materialdesigned to form the gate terminals and the metal coatings which ensurethe ohmic contact with the MOS source and drain regions and with thebase and emitter regions of the bipolar transistor.

BRIEF DESCRIPTION OF THE DRAWING

The above and other objects, features and advantages of my inventionwill become more readily apparent from the following description,reference being made to the accompanying highly diagrammatic drawing inwhich:

FIG. 1 is a circuit diagram which shows the equivalent electricalcircuit of the 4-terminals integrated structures, which the inventionintends to realize;

FIGS. 2-7 are diagrammatic sections which show a structure according tothe invention, in the vertical MOS power transistor version, during thevarious stages of the manufacturing process;

FIG. 8 is a section which shows the structure obtained at the end of theprocess referred to in the previous FIGS. 2-7;

FIG. 9 is a shows a diagram of the concentrations of the various typesof doping agent along a section of the structure of FIG. 7;

FIGS. 10-11 are sections which show a structure according to theinvention, in the horizontal MOS power transistor version, during thevarious stages of the manufacturing process; and

FIG. 12 is a section which shows a schematic representation of thestructure obtained at the end of the process referred to in FIGS. 10-11.

SPECIFIC DESCRIPTION

FIG. 1 shows the equivalent electrical circuit of the 4-terminalintegrated structures that the invention intends to provide.

This circuit consists or a high-voltage bipolar power transistor Tconnected by means of its emitter to the drain of a low-voltage MOSpower transistor P.

The various stages of the manufacturing process of the integratedstructure, in the vertical MOS version, are described hereunder.

A first high resistivity N- conductivity epitaxial layer 2 is grown onan N+ type substrate 1 (FIG. 2). A P+ type region 3 is then obtained, bydeposition or implantation and subsequent diffusion, on said layer 2(FIG. 3). An N+ type region 4 is then obtained by means of the sameprocess (FIG. 4). This is followed by the growth of a second N typeepitaxial layer 5 (FIG. 5) and, by the known procedures of oxidation,photomasking, implantation and diffusion, the creation of the P+ typeregions 8, which enable the region 3 constituting the base of thebipolar transistor to be connected on the surface (FIG. 6). Alow-voltage vertical MOS power transistor and in particular the relativeP conductivity body regions 6, N+ type source regions 7 (FIG. 7), thegate 9 and the metal coatings 10, 11 and 14 for ensuring the ohmiccontact with the regions 6, 7, 8 and the substrate 1 (FIG. 8) are thencreated in the area between the two regions 8, according to knownprocedures.

FIG. 8 shows the final structure, as it appears after addition of theterminals C (collector), B (base), S (source) and G (gate) and theinsulating layer 12 of the gate 9 (said gate being connected to therelative terminal by means of the insulated conductor 13). Regions 1, 2,3 and 4 of the figure constitute, respectively, the collector, the baseand the emitter of a bipolar transistor, while region 5 constitutes thedrain of the MOS. Said drain is consequently connected directly to theemitter of the bipolar transistor thus forming a structure having as itsequivalent circuit the circuit of FIG. 1.

The emitter 4 represents a completely buried N+ type active region; bygrowing a second N type epitaxial layer 5 it is thus possible to connectthe drain of the MOS to the emitter 4 of the bipolar transistor.

The profile of the concentration (Co) of the various types of dopingagent in the different regions of the structure, along section A--A ofFIG. 7, is shown in FIG. 9, where axis x refers to the distance from theupper surface of the structure.

The manufacturing process of the integrated structure, in the horizontalMOS power transistor version, includes the following stages.

A high resistivity N- type epitaxial layer 22, which is designed toconstitute the collector of the bipolar transistor, is grown on a N+type substrate 21 (FIG. 10). Two P+ type regions 23 and 24 are thencreated simultaneously on said layer, by the known processes ofdeposition or implantation and subsequent diffusion, the first of whichbeing destined to act as a base for the bipolar transistor and thesecond to receive the MOS. By means of the known processes of oxidation,photomasking, deposition or implantation and subsequent diffusion, an N+type region 25 which is destined to act as the emitter of the bipolartransistor is created within the region 23, while two N+ type regions 26and 27 which are destined to act as the source and the drain of the MOSare created within the region 24 (FIG. 11). This is followed by theformation of the MOS gate 28, the gate insulating layer 29, the metalcoatings 30, 31, 32, 33 and 34, which are designed to ensure the ohmiccontact with the underlying regions, and lastly the connections to theterminals S, G, B and C (FIG. 12).

The aforesaid metal coatings also include the formation of a track 35for connecting the drain D to the emitter E, so as to achieve theconnection of the two transistors in the configuration of FIG. 1.

In both the vertical MOS and horizontal versions, the final structureobtained is provided with 4 terminals, 3 of said terminals being locatedon one face of the chip and the 4th on the other face.

The described process can obviously be used to simultaneously obtain, onthe same chip, several pairs of bipolar and MOS transistors having acollector terminal in common and their base contacts, sources and gatesconnected to three respective common terminals by means of a metalcoating carried out on the front of the chip at the end of the process.

We claim:
 1. An integrated high-voltage bipolar power transistor andvertical low-voltage MOS power transistor structure, comprising:an N+type semiconductor substrate; an overlying semiconductor layer on saidN+ type semiconductor substrate and comprising a first N type epitaxiallayer and a second N type epitaxial layer grown on said first N typeepitaxial layer; a first dopant-diffusion P type region formed in saidfirst N type epitaxial layer in a vicinity of a boundary between saidfirst N type epitaxial layer and said second N type epitaxial layer; asecond P type region connecting said first P type region with a surfaceof the structure and located in said second N type epitaxial layer, saidfirst and second regions constituting a base region of a bipolartransistor of said structure; a third completely buried N+ type regionadjoining at a lower side said first P type region, substantially moredoped than said second epitaxial layer, located astride said boundarybetween said first and second epitaxial layers, and constituting anemitter region of the bipolar transistor, a portion of said secondepitaxial layer being disposed between said third region and saidsurface with said second region extending alongside said portion of saidsecond epitaxial layer to said surface; body and source regions of anMOS transistor of said structure located in said portion of said secondepitaxial layer in a vicinity of said surface and above said thirdregion spaced from said second P type region; means connected to saidportion of said epitaxial layer between said body and source regions toform from said portion a drain region of said MOS transistor; and meansconnected to said N+ type semiconductor substrate to form from saidsubstrate a collector of said bipolar transistor.
 2. An integratedhigh-voltage bipolar power transistor and horizontal low-voltage MOSpower transistor structure in an emitter switching configuration,comprising:an N+ type semiconductor substrate; an N- type epitaxiallayer grown on said N+ type semiconductor substrate; a firstdopant-diffusion P+ type region formed in said N- type epitaxial layerat a surface thereof and constituting a base of a bipolar transistor ofsaid structure; a second N+ type region formed within said first P+ typeregion and adjoining said first P+ type region at a bottom and sides ofsaid second N+ type region and terminating at said surface to constitutean emitter of said bipolar transistor; a third P+ type region formed insaid N- type epitaxial layer at said surface, spaced from said first P+type region; a fourth N+ type region formed within said third P+ typeregion and adjoining said third P+ type region at a bottom and sides ofsaid fourth N+ type region and terminating at said surface, said fourthN+ type region forming a source of an MOS transistor of said structure;a fifth N+ type region formed within said third P+ type region andadjoining said third P+ type region at a bottom and sides of said fifthN+ type region and terminating at said surface, said fifth N+ typeregion being spaced from said fourth N+ type region and forming a drainof said MOS transistor of said structure; a conductor track on saidsurface connecting said emitter and said drain; and means connected tosaid N+ type semiconductor substrate to form from said substrate acollector of said bipolar transistor. .Iadd.
 3. An integrated circuitdevice structure, comprising, in a substantially monocrystalline body ofsemiconductor between first and second surfaces thereof:a collector,extending to said first surface, which is heavily doped with a firstconductivity type; a drift region, overlying said collector, which hassaid first conductivity type and is more lightly doped than saidcollector; a base region, overlying said drift region, which has asecond conductivity type; an emitter region, overlying said base region,which is heavily doped with said first conductivity type; a drainregion, overlying said emitter region, which has said first conductivitytype and is more lightly doped than said emitter region; a body region,overlying said drain region, which has said second conductivity type; asource region, overlying said body region, which is heavily doped withsaid first conductivity type; a gate electrode which is in proximity tosaid second surface of said monocrystalline body, and which iscapacitively coupled to said body region to induce therein a channelregion which provides a current path from said source region and saiddrain region..Iaddend..Iadd.
 4. The device structure of claim 3, whereinsaid first conductivity type is N-type and said second conductivity typeis P-type..Iaddend..Iadd.5. The device structure of claim 3, whereinsaid gate electrode is insulated from said body region..Iaddend..Iadd.6.An integrated circuit device structure, comprising, in a substantiallymonocrystalline body of semiconductor between first and second surfacesthereof;a VDMOS device, comprising a respective first diffusion of afirst conductivity type in proximity to said first surface of saidmonocrystalline body, and a second diffusion of a first conductivitytype within said body, and a gate electrode capacitively coupled toregulate current flow between said first and second diffusions; ahigh-voltage bipolar device, comprising a respective first diffusion ofa first conductivity type in proximity to said second surface of saidmonocrystalline body, and a second diffusion of a first conductivitytype within said body, and a base electrode interposed to regulatecurrent flow between said first and second diffusions; wherein saidVDMOS device directly overlies said bipolar device, and wherein saidsecond diffusion of said VDMOS device is merged with said seconddiffusion of said bipolar device..Iaddend..Iadd.7. The device structureof claim 6, wherein said first conductivity type is N-type and a secondconductivity type is P-type..Iaddend..Iadd.8. The device structure ofclaim 6, wherein said gate electrode is insulated from said bodyregion..Iaddend..Iadd.9. A merged power transistor structurecomprising:a first active device located near a first surface of amonolithic semiconductor body, and providing conduction between saidfirst surface and a first buried layer of a first conductivity type,whose potential is controlled by said conduction of said first activedevice; and a second active device located within said monolithic bodybeneath said first device, and providing bipolar conduction between saidfirst buried layer and a second surface of the monolithic body; saidsecond active device including a second buried layer, beneath said firstburied layer, which forms a base-emitter junction with said first layer;conduction of said first device controlling the bias of saidbase-emitter junction, and thereby controlling conduction of said secondactive device; whereby said first active device provides control ofcurrent, and said second active device provides high-voltage standoffwith low on-resistance..Iaddend.